Dynamic MOS memory technology has continually advanced by periodic increases in storage density since its commercial inception. As DRAMs move into the 16-Mbit density and beyond, the physical structures used in integrated circuit technology have been continually scaled to meet the density requirements.
The effects of dynamic line-to-line coupling on the nominal available data sense signal has long been recognized in DRAM design. Folded bit-line architecture, see for example RE 32,708 to Itoh, has been used in 256-Kb, 1-Mb, 4-Mb and 16-Mb DRAM designs for commonmode noise rejection caused by word line noise, plate bounce and substrate bounce disturbances. The distance between bit lines has shrunk from 3 microns in the 1-Mb generation to less than 0.5 microns for a 64-Mb design. To a great extent, as structures are scaled down, the electrical effects inherent in the technology are also scaled. In some instances there are some variables which cannot be scaled to the same degree as others. Vertical scaling cannot be fully utilized to offset this problem because resistance and electromigration considerations limit the extent to which scaling of conductors can be implemented. Such lack of scalability causes previously insignificant parameters to become more and more of a problem. As Physical dimensions are reduced to the sub-micron range, factors like line-to-line capacitive coupling are becoming a significant cause of sense signal loss and must be compensated for in circuit designs. A number of circuit innovations have been implemented throughout the history of DRAM technology including such features as dummy or reference cells, differential sensing and folded bit lines. All of these features have become critical in DRAM designs.
As designs for 16- and 64-Mbit are planned it has become apparent that the once-ignored line-to-line capacitance noise will be a dominant signal detractor. Although the material, and thus physical shape and profile, of data bit lines can have a significant effect on line-to-line coupling, the physical spacing of these lines will have the most significant effect on noise. Cottrell and Buturla, in their paper, "VLSI wiring capacitance," IBM J. RES. DEVELOP. VOL. 29, May 1985, pp. 277-288, have shown that line-to-line capacitance for a line separation of 1.0 micron amounts to more than 45% of the total capacitance of the line. Capacitive line-to-line coupling has been increasing dramatically in DRAM memory technology as improvements in lithography have permitted manufacture of conductors with submicron separation. This increased dynamic line-to-line coupling has become a major noise problem in DRAM array design and new circuit techniques are needed to obtain maximum signal levels and sense-amp sensitivity in a high speed DRAM.
One of the earliest techniques to reduce crosstalk between adjacent bit lines is described in the article "FET Stray Coupling Capacitance Equalization Technique," by Sonoda, IBM Technical Disclosure Bulletin, Vol. 17, No. 5, October 1974, p. 1355. This technique, known as twisted bit line architecture, physically interchanges or crosses adjacent complementary data bit lines so that equal portions of an adjacent pair of bit lines will receive compensating coupling noise. Twisted lines have also been used to reduce data line crosstalk. All twisted techniques involve the concept of alternating the physical positions of pairs of bit lines to achieve varying degrees of common mode noise rejection. One of these approaches, the modified twisted bit line, crosses bit lines associated with the same data bit and also crosses bit lines with a different data bit so that the twisting can cancel noise from between a bit-line pair and from adjacent bit lines from neighboring bit-line pairs. Such schemes require multiple levels of interconnect and associated contact area. These techniques are generally described in the article, "Twisted Bit Line Architectures for Multi-Megabit DRAM's," H. Hidaka et al., IEEE J. Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 21-27.
In practice, some problems exist in implementing twisted bit line architecture. One such problem is that three levels of conductor interconnect must be available to implement the required cross-overs needed for twisting. If the cross-overs are not to impact array cell density, they must be implemented at minimum conductor pitch. If the required bit line twists can be physically implemented, almost certainly there will be wasted silicon area due to the requirement of regular, usually four, breaks in the array area to implement the twists. Due to an increase in the complexity of the wiring and to an increase in the number of contact interfaces, reliability is seriously impacted.
Finally, the implementation of bit line twist increases the actual capacitance of the bit lines, somewhat negating its benefit.
Thus, in accordance with this invention, problems associated with diminishing bit line spacing in advancing DRAM technology, specifically that of increasing line-to-line capacitance, are easily solved without complex wiring techniques proposed by others. The disclosed shielded bit line array architecture eliminates the signal development noise and sense-amp set noise caused by dynamic line-to-line coupling without impact on density and yield found with twisted bit line architectures. Signal margin of the SBL array is further enhanced because a sense latch in a SBL array requires 76% less signal to set correctly than the folded array.
Accordingly, it is an object of this invention to improve the signal to noise ratio of data signals in high density DRAMs.
Another object of the invention is to increase the available signal margin in DRAM sensing circuits.
Yet another object is to improve the reliability of high density DRAMs by reducing the complexity of array wiring necessary to achieve reliable operation.